Stress-induced via bottom voiding is a fatal reliability issue commonly encountered in typical copper low-k dielectric interconnect structures. The formation of voids at the bottom of the vias results from the stress gradient distributions in the copper/low-k dielectric interconnect structures, vacancies in the grain boundary of the electroplated copper, and the capability of the vacancies to diffuse through the material.
In general, the stress gradient drives the vacancies toward the via bottom through the pathways of copper grain boundary and the interfaces of copper and the underlying etch stop layer. For a given reliability and thermal stress/test condition, such as 175° C. and 500 hours, there is a characteristic property, namely the effective vacancy diffusion area, that can characterize the effective copper area within which vacancies will be driven to the via bottom and form potentially fatal voids.
Therefore, the effective vacancy diffusion area is unique for a given silicon processing baseline and can be used to derive many design rules for a given technology node. Currently, a clear index of the metallization quality of a certain baseline process cannot be obtained. As a result, there is a need for a test pattern that can be used to derive the effective vacancy diffusion area for a given baseline process and technology node.